1. Field of the Invention
This invention relates to a serial interface embedded in a one-chip LSI circuit together with a processor and, more particularly, to an improvement in a data input/output control device for a transfer of data between the processor and an external apparatus.
2. Description of the Related Art
Conventionally, the serial interface embedded in a one-chip LSI circuit together with the processor is operated at processor clock for the processor when the transfer of data is conducted between the processor and an external apparatus, such as by synchronizing a signal input to the serial interface (a data transfer clock and signals necessary for the transfer of the data from the external apparatus) with the processor clock.
The conventional serial interface is described hereunder with reference to FIGS. 1, 2, and 3.
Construction of a conventional serial interface, the processor and the external apparatus are shown in FIG. 1. The serial interface is equipped with structure to perform data input/output control and input/output data transfer. The input/output control is accomplished for all the units within the "data input/output device" dashed lines. The output buffer 530, shift register 540, and input buffer 550 perform input/output data transfer and are contained within the "data transfer device" dashed lines.
Data is transferred to and from an external apparatus 500. Transmission of a reception of the data is conducted between the external apparatus 500 and the embedded-type serial interface equipped with the devices labelled with numeral references above 500.
A transfer clock 501 is supplied from the external apparatus 500.
A transfer control signal 502 shows that the transfer of the data to the external apparatus is ready.
A processor 503 stores the data inputted from the external apparatus 500 or executes an operation.
A processor clock 504 is for an operation of the processor 503.
A controller 510 outputs control signals, which is synchronized with the processor clock 504.
A ready signal 511 is outputted from the controller 510 to show that the input or the output of the data is ready.
A synchronization means 521 synchronizes the transfer clock 501 with the processor clock 504, which is shown in a time chart of FIG. 2.
A synchronization means 522 synchronizes the transfer control signal 502 with the processor clock 504, which is shown in a time chart of FIG. 3.
A clock 523 is synchronized with the processor clock 504 by the synchronization means 521.
A signal 524 is outputted from the synchronization means 522.
An output buffer 530 holds the data of n bits (n is a positive integer) transferred from the processor 503 to the external apparatus 500.
A shift register 540 obtains the data of n bits outputted from the output buffer 530, which is synchronized with the clock 523 is accordance with a transmission data load signal outputted from the controller 510. The shift register 540 shifts the data in a direction of the most significant bit (MSB) by one bit at one time which is synchronized with the clock 523 in accordance with a shift clock signal.
One-bit data 541 located at the MSB of the shift register 540 are outputted to the external apparatus 500.
One-bit data 542 from the external apparatus 500 are inputted to the least significant bit (LSB) of the shift register 540.
An input buffer 550 obtains the data of n bits held in the shift register 540, which is synchronized with the processor clock 504 in accordance with the shift clock signal outputted from the controller 510.
A down counter 560 is set with an initial number m (0&lt;m.ltoreq.n; m is an integer) for a start of a count down of the bits in the data to be inputted or outputted, and reduces m by one at a timing of the clock 523.
A flag circuit 570 with a flag showing status of the output buffer 530 and the input buffer 550 is set with a set signal 571 output from the controller 510 and is reset with a reset signal 572 outputted from the processor 503, the set signal 571 and the reset signal 572 being synchronized with the processor clock 504.
The serial interface constructed as described above is operated to output the data or input the data. The operations are described hereunder with reference to FIGS. 1, 2, and 3 (reference can also be made to "MN 19011, 1909 LSI Manual" by Matsushita Electronics corporation.